The present invention relates generally to a logic signal display apparatus, more specifically, to an apparatus for displaying, a logic signal on a raster scan type display device associated with a logic analyzer or the like.
In various kinds of electronic apparatus, logic signal processing techniques are increasingly popular as a result of development of microprocessors and computers. Oscilloscopes, logic probes and logic analyzers are utilized for developing, calibrating and trouble-shooting any electronic apparatus using logic circuiting techniques. In addition, logic analyzers are ideal as a measurement instrument for such an electronic aparatus, because they can store multi-channel input logic signals (data) in a memory, such as random access memories and can display the data, stored in the memory, on a display means, such as a cathode ray tube (CRT), so that the data, before trigger signal occurrence, can be measured. There are two display modes in logic analyzers, one being a timing display mode for displaying the logic signal as a signal waveform, and the other being a state display mode for displaying the stored data as alphanumerics of words, such as binary, octal and hexadecimal.
A raster scan type display device is suitable for the display means of logic analyzers, since the raster scan type display device can display the data in both timing and state display modes, and is flicker free even if a great deal of information is displayed. Moreover, a raster scan type display device is capable of inverting black and white with respect to the entire display or a partial display and blinking the display.
For displaying the logic signals in the Timing Display Mode using the raster scan type display device in a conventional manner, the display waveform patterns must be previously stored in a waveform display read only memory (ROM). When the input logic signal is displayed as the timing waveform on the CRT, a code signal of the waveform pattern (stored in the ROM), corresponding to the input logic signal, is stored in a random access memory (RAM) as FONT information (corresponding to an address of the ROM), and the waveform pattern stored in the ROM is read out in accordance with the FONT information stored in the RAM. Since the prior art must store all kinds of the waveform patterns for the display waveform in the ROM, a large capacity ROM is needed. A large capacity ROM is expensive. If a logic waveform segment (FONT) consists of many waveform elements, the variety of the waveform patterns increases and a much large capacity is needed for the ROM. On the other hand, if a number of the elements for the waveform segments is decreased thereby decreasing the number of the waveform patterns to be stored in the ROM, the display RAM requires a larger capacity (since a large number of the waveform patterns, namely, the FONT information, must be stored in the display RAM.)
FIG. 1 shows a model of the timing waveforms of the logic signals displayed in the raster scan system. For simplifying an explanation of FIG. 1, four channels (CH1 through CH4) are displayed, and each channel display includes three raster scan lines (1, 2, 3) and consists of seven waveform segments (FONTs). In other words, one waveform segment consists of 3.times.3 bits. Raster scan lines (A, B, C) of FIG. 1 are provided to separate the channels from one another.
Sixteen kinds of the waveform patterns, such as A through P of FIG. 2, have to be stored in the ROM for displaying FIG. 1 in a conventional manner. Assuming that the horizontal bit number of each waveform segment is three bits, and transitions occur every three bits, rising and falling edges (transitions) cannot be displayed. Thus, the widths of the rising and falling edges must be narrower than that of the logic level (one bit). For making the widths of the rising and falling edges a half width of one logic level, six bits are necessary for each segment in the horizontal direction, and the ROM must have a large capacity.